1. Field of the Invention
This invention generally relates to phase-locked loop (PLL) circuitry and, more particularly, to a system and method for simply determining the frequency of a signal with respect to a known reference frequency.
2. Description of the Related Art
In many communication applications, the most critical process in determining device performance involves ascertaining the relationship among key frequencies. This complex process limits device performance with regard to speed of acquisition, power consumption, and integrated circuit (IC) die area.
In all PLLs, an internal oscillator is calibrated such that its frequency is exactly identical to an external reference. Modern PLLs consist of an oscillator which can be digitally calibrated. This oscillator is called a digitally calibrated oscillator (DCO). A mechanism is required to identify a digital control value that produces a DCO oscillation with frequency close to the external reference. The mechanism, called frequency band search (FBS), must be simple, such that implementation is cost competitive. Speedy convergence is also highly desirable for fast PLL lock time.
FIG. 8 is a flowchart illustrating a process for acquiring a frequency band in a multi-band communication system (prior art). The PLL is ubiquitous in communication systems. Communication devices, e.g., serializer/deserializer (SERDES) devices, that operate over a wide range of frequencies require several PLLs or DCOs.
The frequency band search begins in Step 800. In Step 802 a comparison is performed between the frequency of the reference and a divided-down oscillator frequency. The result is then analyzed in Step 804. If the reference frequency is close enough to the divided-down oscillator frequency, FBS concludes in Step 808. Otherwise, the digital control of the oscillator is adjusted in Step 810 and a comparison is performed again (Step 802). A frequency band search across a band of several oscillators can be very time consuming, especially if the communication frequency band is unknown.
FIG. 1 is a schematic block diagram of a frequency counter (prior art). When reset b is released, both counters start to accumulate. The most significant bit (MSB) of each counter rises when the corresponding clock finishes counting 27 clock cycles. If the compClk is faster than refClk in frequency, compMSB rises before refMSB. The Edge Detector 100 identifies the relative time of the rising edge of compMSB and refMSB. CompFast rises if compClk is faster than refClk. However, this method requires a large number of clock cycles to make a comparison, especially if the two clocks are close in frequency. Long measurement times slow PLL frequency acquisition.
Going forward, fast lock times with large pull-in range bandwidths are going to be a required feature of modern PLL and clock and data recovery (CDR) for wired and wireless serializer/deserializer (SerDes) applications. In wired SerDes applications, the demand for multiple protocols with dynamic adaptation has pushed the fast lock requirement so that network protocol change can occur in real-time. In wireless SerDes, the demand for a new generation of data wireless networks has pushed the fast lock requirement so that data can be adapted with multiple rates.
It would be advantageous if there was a means to identify an input signal with an unknown frequency within a narrow frequency range (band), for the purpose PLL/CDR frequency acquisition applications.